The present invention generally relates to wafer processing systems within a semiconductor processing facility and, more particularly, to decreasing wafer processing cycle time by predicting and correcting processing delays that can occur downstream from the current wafer processing location.
A conventional semiconductor processing plant typically includes multiple processing areas or bays interconnected by a path, such as a conveyor belt. Each bay generally includes the requisite processing tools to process semiconductor wafers for a particular purpose, such as photolithography, chemical-mechanical polishing or chemical vapor deposition, for example. Material stockers or stocking tools generally lie about the plant and store semiconductor wafers waiting to be processed. Each material stocker typically services two or more bays and can hold hundreds of cassettes. The wafers are usually stored in cassettes and then disposed within a carrier that moves the wafers from processing location to another. The carriers are usually tracked by their carrier code by a computer system as they move through the plant.
Once a wafer lot has been retrieved, and the equipment has been set up, the processing on the wafers by a particular piece of equipment, or xe2x80x9ctool,xe2x80x9d can begin. At this point, the wafer lot is xe2x80x9cmoved-inxe2x80x9d to the processing location. An operator on the line then communicates this information to the host computer. The wafer lot remains in this state until processing is completed. The operator then must perform tests and verifications on the integrity of the wafers. When all tests and verifications have been performed, the host computer application program must be notified. Wafers may have moved from one cassette to another as a result of wafer processing; therefore the host application and computer have to be notified of these moves. The operator then places the cassette of xe2x80x9cmoved-outxe2x80x9d wafers in the material stocker to await orders as to where the wafers will be sent next.
The semiconductor processing plant, including the bays, material stockers and an automated material handling system, generally operates under control of a distributed computer system running a factory management program. In this environment, the automated material handling system (AMHS) conceptually includes the cassettes, pods and the transportation system. An empty carriers management system and a separate test wafer management system are usually included and integrated into the AMHS. One of the goals in moving wafer lots from one processing location to another in a processing plant is to do so in a manner that will reduce overall processing cycle time. Unfortunately, situations such as improper factory management software and tooling setups, the use of incorrect software in tooling or the use of outdated software versions in tooling at a certain processing location tend to increase cycle times for wafer processing while the situation is corrected.
The present invention is directed to addressing the above and other needs in connection with decreasing cycle time in wafer processing by predicting and correcting downstream processing delays before a wafer lot is released to the next processing location. The invention also addresses issues that include improper setups with respect to equipment interfaces, network systems, other factory systems, improper software versions and incorrect recipes.
According to one aspect of the invention, it has been discovered that wafer processing cycle times are reduced when downstream processing locations are polled, prior to arrival of a wafer lot, to determine if the downstream processing location is prepared to receive the upcoming wafer lot. Any incompatibilities or anomalies are addressed immediately to ensure that wafer lots are moving through the processing line without delays or diversions of material.
According to another aspect of the invention, a method for forecasting processing delays in a semiconductor processing facility having a material handling system includes presenting a wafer lot to a first application processing location. The first processing application is then applied to the wafer lot and a set of first application processing results for the wafer lot is then generated and communicated to a second application processing location. The second application processing on the wafer lot is then simulated based on the first application results in order to determine availability status of the second processing location to receive the wafer lot. The availability or operating status of the second processing location is then communicated to the material handling system, the material handling system communicating instructions to the first processing location on where to send the wafer lot after the simulation is complete.
In yet another aspect of the invention, a method of verifying downstream processing line readiness in a semiconductor processing facility having a material handling system includes presenting a wafer lot to a first application processing location. A signal is then sent to a second application processing location to verify readiness by simulating the second application processing on the wafer lot. The operating status of the second processing location is then communicated to the material handling system, the material handling system communicating instructions to the first processing location on where to send the wafer lot after the simulation is complete.
In yet another aspect of the invention, a system for forecasting processing delays in a semiconductor processing facility includes a material handling system for presenting a wafer lot to a first application processing location. A processing tool applies the first application to the wafer lot and measurements are taken to generate set of first application processing results for the wafer lot. A communications module communicates the first application results as data to a second application processing location. A simulation module simulates the second application processing on the wafer lot based on the first application results in order to determine the availability status of the second processing location to receive the wafer lot.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures in the detailed description that follow more particularly exemplify these embodiments.